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MLX90255
Linear Optical Array Application Note: MLX90255 Demo Board
The demo board described in this document facilitates the evaluation of the MLX90255xx Linear Optical Arrays. The board provides the necessary timing and clock signals to support both the on-board imaging device or an externally connected sensor. The designer is then free to investigate the properties and performance of the device without having to design and construct an external support circuitry. A regulated DC power supply between 6 and 10V is the only input signal. An oscilloscope is required for observation and analysis of the output signals.
Features and Benefits
* * * * * * * * 128 x 1 Sensor-Element Organization (1 Not Connected, 1 dummy, 128 real, 1 dummy, 1 Dark Pixel) 385 DPI sensor pitch High Linearity and Uniformity for 256 Gray-Scale High Sensitivity: 1.7V @ 10W/cm 2 @ 0.7ms integration time Special Gain Compensation for use with single LED light source Output Referenced to Ground Single 5V Supply Operation to 1MHz
Applications
* * * position Sensing electrical Power Assist Steering (EPAS) spectrometer Applications
Functional Diagram
General Description
The MLX90255xx linear sensor array consists of a 128 x 1 array of photodiodes, associated charge amplifier circuitry and a pixel data-hold function that provides simultaneous integration start and stop times for all pixels. The pixels measure 200m (H) by 66 m (W) and there is 8 m spacing between pixels. Operation is simplified by internal control logic that requires only a Serial Input (SI) pulse and a clock signal. The sensor consists of 128 photodiodes arranged in a linear array. Light energy falling on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. The output and reset of the integrators is controlled by a 132-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI. This causes all 132 sampling capacitors to be disconnected from their respective integrators and starts an integrator-reset period.
MLX90255 Linear Optical Array
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MLX90255 Pin Description
Pin Number SMD8 1 2 3 4 5, 6, 7, 8 GLP5 1 2 3 4 5 SI CLK A0 VDD GND Serial Input. SI defines the end of the integration time and the start of the data out sequence Clock. The clock controls the charge transfer, pixel output and reset (together with SI) Analog output Supply Voltage, for both analog and digital circuits Ground. All GND pins are referenced to the substrate. Symbol Description
Schematics
JP1 R2 JP2 2 1 CONN PWR 2-H 1 1N4001 + C6 22uF/16V U2 C78L05/TO92 D4 2 POWER 3 IN GND OUT 1 680 LED + C7 10uF/16V SI CLK VOUTB R5 330 5V 5V 5V R3 330 1 2 3 4 5 5V LED D2 5V VOUTA SI CLK 1 2 3 4 5 90255 External U3 C8 100n C4 220n SI CLK VOUT VDD VSS 90255 SMD
2
D3 LED
R1 10k U1 RESETB CLK SI 1 2 3 4 5 6 7 8 9 10 RESET PD0(RxD) PD1(TxD) XTAL2 XTAL1 PD2(INT0) PD3(INT1) PD4(T0) PD5(T1) GND Vcc PB7[SCK) PB6[MISO) PB5(MOSI) PB4 PB3(OC1) PB2 PB1[AIN1) PB0[AIN0) PD6(ICP)
C5 100n SW1 1 2 3 6 5 4
R4 1k C1 100n
XTAL2 XTAL1 LED Y1 10MHz C2 22p C3 22p
20 19 18 17 16 15 14 13 12 11
FREQ4 FREQ3 FREQ2 FREQ1 INT4 INT3 INT2 INT1
SW Freq
SW2 1 2 3 SW Int 6 5 4
AT90S2313
TP4 CLK 1 SI
TP3 1 TEST POINT TP6 TP5 VOUTA 1 TEST POINT 1 GND 5V TP1 1 5V Supply
TEST POINT TP2 VOUTB 1
TEST POINT
Functional Description
The demo board mainly consists of the following blocks: * 5V regulator with a power-on indication LED * general purpose microcontroller with reset circuitry and crystal oscillator * 2 rotary DIL switches for changing settings * a LED which lights up if the chosen settings MLX90255 Linear Optical Array
are out of the device specification 1 on-board MLX90255 sensor (B) and a 5pins connector for an external device (A) * test terminals for all important signals The different blocks can easily be found in the schematic diagram. * The main purpose of the demonstration board is to provide a specified clock frequency and an
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appropriate SI pulse to the optical array. The required pull-down resistors are also foreseen on the board. All important signals (SI, CLK, VOUT, 5V and GND) are connected to test terminals, which makes it easy to visualize them on an oscilloscope. One sensor in a SMD package is soldered on the PCB (called B) while an external sensor can be connected to the 5pins connector row (upper right corner) (called A). Both output signals are connected to test terminals, called respectively VOUTB and VOUTA. An external regulated DC power supply, with an output voltage between 6 and 10V, needs to be connected to the screw connector in the upper left corner of the PCB. A regular 9V battery is also possible. (Mind the sign!) As soon as the power supply is switched on, a LED lights up and the micro controller starts generating the CLK and SI signals with the selected frequency and integration time. The frequency of the signal CLK can be chosen with the rotary DIL switch on the right. The frequencies corresponding to the 16 positions of this switch are shown in the following table. Position 0 1 2 3 4 5 6 7 8 9 A B C D E F CLK frequency 36kHz 64kHz 77kHz 93kHz 112kHz 141kHz 170kHz 214kHz 284kHz 345kHz 435kHz 588kHz 909kHz 1.0MHz 1.25MHz 1.67MHz generated with the selected frequency, and after them the CLK line is pulled low until the next SI pulse. See further in this document for the correct timings. The light integration time can be selected with the other rotary DIL switch. Again 16 positions are possible, however now there is no one-toone relation with the corresponding integration times. Actually the switch specifies a time which rd starts only after the 133 CLK pulse. As the th integration time already starts after the 18 pulse (see device specification), the total integration time also depends on the selected frequency. The following table shows for each position (of the `integration time switch') the minimal and the maximal integration time, corresponding to respectively the maximal and the minimal CLK frequency. Position 0 1 2 3 4 5 6 7 8 9 A B C D E F Total Integration Time Minimal 79us 230us 380us 682us 985us 1.30ms 2.50ms 3.10ms 3.85ms 4.60ms 6.10ms 7.7ms 9.15ms 10.5ms 15ms 20ms Maximal 3.17ms 3.33ms 3.48ms 3.77ms 4.09ms 4.40ms 5.60ms 6.20ms 6.95ms 7.70ms 9.15ms 10.7s 12.5ms 10.5ms 15ms 20ms
The analog output voltage is directly proportional to the light intensity and the integration time up to the devices saturation level (3V typical). The response of a pixel can be described with the following formula: VOUT = PR*Plight + offset + PRerror*Plight + DC where DC means the dark current. The proportionality constant PR is the responsivity of the device given in (V*cm2/W*sec). Responsivity is wavelength Rev 1.0 31-May-01
Positions 0, E and F correspond to frequencies that are outside the device specification. Lighting up a second LED indicates selecting one of them. For each SI pulse, 133 CLK pulses are
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dependent. For the MLX90255 the responsivity will peak at about 770nm.
Timing diagram
The first scan after power up is incorrect: the chip needs 1 SI pulse and 133 CLK pulses to initialize the complete device. The second SI pulse is valid and starts the integration time after 18 clock pulses (see device specification). A next SI pulse ends the integration time, and the pixel values are scanned out to the output pin at the rate of CLK. Note that it is perfectly possible to stop the CLK rd pulses after the 133 . After each SI pulse, 133 CLK pulses are necessary however. When an SI pulse is given the chip always does 2 things: * It clocks out the former data of the pixels to the OUT pin, at the rate of the CLK signal. * The device is in a reset state until the falling th edge of the 18 CLK pulse. At that moment the integration time starts.
Bill of Materials for the demo
* * * * an MLX90255 demo board with on-board sensor device optionally an external device connected to the 5 pins header a regulated power supply (6...10VDC) an oscilloscope
Operation
To operate the demo board the following steps are necessary: * apply 6...10VDC to the board * connect an oscilloscope probe to the VOUTA or VOUTB pin (depending on the actual device of interest) and the scope ground to the GND terminal * connect a second oscilloscope probe to the SI terminal, and use this channel as a triggering input * select the appropriate integration time and CLK frequency. If the amount of impinging energy is relatively large, a short integration time is necessary to prevent complete saturation of the output.
Some oscilloscope screenshots to make it even more clear.
Integration Time
1st SI pulse
2 nd SI pulse
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In the first figure, one can see clearly a first SI pulse, followed by 133 CLK pulses. After the selected integration time, a next SI pulse is generated, again accompanied with 133 CLK pulses. Note that the CLK pulses have stopped. During the CLK pulses, the pixel values of the former integration time are clocked out. This screenshot repeats itself continously for every new scan. Note that this figure does not show the initialisation scan (very first scan), as this is only necessary after Power Up. These pictures were taken during continuous operation. The second screenshot shows a zoom of the first one. Here the SI pulse together with the first CLK pulses is clearly visible. The first pixel has a low value, as this is an unconnected pixel. (The last one is connected, but covered with metal.)
1.
2.
Note
In a real-life application two different timing solutions are possible, depending on the overall system specification and performance.
Continuous read-out. SI pulses are generated in a regular and controlled time frame. For each SI pulse, the integration time is controlled and the data at the output of the sensor is valid. This requires a highspeed microcontroller, as it has to handle this high throughput of data. Continuous read-out can also be used if the algorithm requires only a very limited amount of calculation. `Burst-like' read-out. If the application needs a long time for data manipulation, the system cannot control the integration time for each SI pulse. SI pulses aren't generated in a regular time frame corresponding to the necessary integration time. The first SI pulse after a longer calculation intensive part, results in useless data as the integration time was not precisely timed, so the sensor will be completely saturated. After the desired integration time, a second SI pulse is generated, and the valid data is clocked out.
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